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| Module Availability |
| Autumn Semester |
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| Assessment Pattern |
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Unit(s) of Assessment
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Weighting Towards Module Mark( %)
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Written examination
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60%
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Two design assignments involving VHDL coding and FPGA implementation, which are issued in weeks 2 and 6
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40%
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| Module Overview |
This module provides knowledge about advanced digital circuit design and the hardware description language VHDL. The practical part of the course is concerned with FPGA implementation using modern CAD tools. |
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| Prerequisites/Co-requisites |
| EEE2025 Electronics V |
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| Module Aims |
- Develop understanding of digital circuit design using the hardware description language VHDL.
- Give insight into current approaches to application-specific integrated circuit implementation and typical design flows.
- Provide hands-on design experience with the main stages of a typical ASIC/FPGA design flow.
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| Learning Outcomes |
By the end of this module, students would be expected to be:
- familiar with principles of advanced digital circuit design;
- equipped with knowledge and skills allowing them to build FPGA designs using the hardware description language VHDL;
- aware of state-of-the-art ASIC/FPGA design methodologies and CAD tools
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| Module Content |
[1] Introduction. The evolution of VLSI circuits. The role of computer-aided design automation.
[2-4] Hardware Description Languages. Basics of VHDL. Domains and levels of modelling. System specification: Design units. Signals. Behavioural Modelling. Structural Modelling. Hierarchical modelling concepts. Components of a simulation. Testing a design with a Testbench. Lexical elements. Operators. Syntax descriptions – EBNF. Types. Assignments. Processes. Configurations. VHDL synthesis. Examples of VHDL code.
[5-6] Introduction to design assignment 1.
[7-14] Combinational logic design with VHDL. Decoders. Encoders. Three-state devices. multiplexers. Exclusive-OR gates and Parity Circuits. Comparators. Adders, Subtractors, and ALUs. Combinational multipliers. Examples.
[15-21] Sequential-circuit design with VHDL. Latches and flip-flops. Clocked synchronous state-machine design. Feedback sequential-circuit design. Counters. Shift registers. Introduction to design assignment 2.
[22-23] ASIC Design Methodologies and CAD Tools. Design automation and classes of design tools. Implementation approaches. Field-programmable gate arrays. Intellectual property cores. System-on-a-chip. Design synthesis and levels of abstraction.
[24] Revision lecture
Practical Work: The lecture course is accompanied by a set of laboratory exercises on digital design using the hardware description language VHDL. The laboratory work covers all stages of the FPGA design process and involves hands-on exposure to the CAD tools Active-HDL/ModelSim, XILINX ISE, Synplify and a prototyping board (containing a XILINX Spartan FPGA).
The practical component is used as a project-driven learning vehicle in the course. The students learn and discover new knowledge by carrying out design assignments. Being given the general principles of VHDL in lectures, they learn further details about the language and the design tools through hands-on experience being guided by computer-aided learning materials, design tutorials and laboratory supervision. |
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| Methods of Teaching/Learning |
| Lectures (24 hours) and laboratories |
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| Selected Texts/Journals |
Ashenden, P. The Student's Guide to VHDL,1998, Morgan Kaufman Publishers, ISBN 1-558-60520-7, A
Rabaey, J.M. Digital Integrated Circuits. A Design Perspective, 2003, 2nd edition Prentice Hall, ISBN 0-13-120764-4, A
Wakerly J.F., Digital Design Principles & Practices , 2006, 5th ed., Prentice Hall , ISBN 0-13-186389-4, A
Zwolinski, M. Digital System Design with VHDL, 2000, Prentice Hall, ISBN 0-201-36063-2, B
Smith, M.J.S. Application-Specific Integrated Circuits, 1997, Addison-Wesley, ISBN 0-201-50022-1, C
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| Last Updated |
12 August 2010 |
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