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2010/1 Module Catalogue
 Module Code: EEE3021 Module Title: SILICON DEVICE TECHNOLOGY
Module Provider: Electronic Engineering Short Name: EE3.SDT
Level: HE3 Module Co-ordinator: KIRKBY KJ Prof (Elec Eng)
Number of credits: 15 Number of ECTS credits: 7.5
 
Module Availability

Autumn Semester
Assessment Pattern

Unit(s) of Assessment
Weighting Towards Module Mark( %)
Written examination
100%

Module Overview
To understand the processes used in the manufacture of integrated circuits in silicon, encompassing the latest research and developments and looking at future developments
Prerequisites/Co-requisites
Module Aims

To provide an understanding of the technology used to fabricate modern semiconductor integrated circuits.
Learning Outcomes

The course has been designed to provide an up to date view of the technology used in the semiconductor industry, including future trends.  The course will concentrate on silicon since more than 95% of the microelectronics industry is based on this material.  Students completing the course will have acquired knowledge sufficient for them to describe in detail (a) the major process steps used in the manufacture of modern devices and integrated circuits, (b) the order in which the various steps are performed (c) the problems faced by industry in making future generations of devices and circuits.
Module Content

Technology – Processes (15 hours)

 

[1-4]   Introduction, Miller indicies, crystal growth, Czochralski technique

 

[5,6]   Oxidation, SOI, SIMOX, Smartcut technologies

 

[7]      Diffusion in silicon

 

[8-13] Ion implantation – introduction to theory, profiles, damage, doping, annealing, equipment, characterisation of implanted layers, ultra shallow junctions, preamorphisation and solid phase epitaxy; co-implantation; defect engineering; developments for future technology nodes

 

[14]   Tutorial problems

 

[15]    Revision

 

 

Technology – Device fabrication and integration (15 hours)

 

[1]   History of IC fabrication

 

[2]   Moore ’s Law, device scaling, ITRS

 

[3]   Basic technology for n-MOS logic gate

 

[4]   MOSCAP, threshold voltage for MOSFETs

 

[5]     RTP (RTA, RTO, epitaxy, CVD)

 

[6-8]  Basic process steps:

 

             (a) channel stop.  Isolation

 

             (b) salicide process, gate material, channel doping

 

             (c) short channel effects, hot electrons, LDD, LATID, Halo implants

 

[9-13]   CMOS Technology

 

             (a) latchup, well engineering, examples of processes, gettering

 

             (b) shallow junction formation: ultra-low energy implantation, preamorphisation

 

             (c) alternative ion species to B and As, low temperature processing, spike annealing, ramp rate

 

[14]     Tutorial problems

 

[15]      Revision
Methods of Teaching/Learning
Lectures, 30 hours at 3 hours per week
Selected Texts/Journals
[1] S M Sze, VLSI Technology, 2nd edition, McGraw-Hill, 1988
[2] CY Chang and S M Sze, ULSI Technology, McGraw-Hill, 1996
[3] S Wolf and R N Tauber, Silicon Processing for the VLSI Era, Vol 1 – Process Technology, 2nd edition, Lattice Press, Los Angeles, 2000
[4] S M Sze, Semiconductor Devices, Physics and Technology, 2nd edition, John Wiley, 2002

[5] S A Cambell, The Science and Engineering of Microelectronic Fabrication, 2nd edition, Oxford Univ Press, Oxford, 2001

Last Updated

12 August 2010