A: UNIPROCESSOR ARCHITECTURES
[1-5] Real Memory topics
Static and dynamic memory devices – timing and functionality.
Dual–port static memories.
Multiplexing of address and data buses, timing considerations, control lines, etc.
Memory block mapping and interleaving.
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[6-10] Virtual Memory
General principles of paging, segmentation and mixed pages & segmented schemes.
Hardware support – write through, associative memory, cache, etc.
Software Support – page–table maintenance, paging process, etc.
Translation look–aside buffers.
Microprocessor implementations of virtual memory
[11-16] Memory Caches
Direct–mapped, set associative and fully–associative caches.
Cache performance-the effects of different cache memory sizes, individual line sizes, bus width and bit rates.
Cache consistency in a multi-master environment.
[17-25] Instruction Sets and pipelining
General requirements of an instruction set.
Comparison of instruction formats on common processors (from 1st-generation microprocessors through to RISC machines).
RISC vs CISC architectures.
Pipelined processing of instruction streams.
The effect of branch instructions.
Data hazards and avoidance techniques.
Effects of instruction re-ordering and loop unrolling.
Introduction to “Very Long Instruction Word” (VLIW) architectures.
B: PARALLEL ARCHITECTURES
[26-30] Fundamentals
Classifications of parallelism; load balancing; Algorithmic, Geometric and Processor Farming techniques.
Flynn's classification.
Point-to-point interconnection topologies; inter-processor routing schemes.
Amdahl's Law;
Deadlock, and how to avoid it.
Limits to Uniprocessor Performance.
[31-36] Specific Examples
Vector Processors; memory interleaving; vector stride
Very Long Instruction Word (VLIW) architectures.
Beowulf Clusters
Active Memory architectures: AMT DAP; Thinking Machines CM-1, CM-2.
Virtual Shared Memory architectures: CM-5; Cray T3D; Kendall Square KSR-1.
Quantum Information/Computing
